Table 15-6. Cmp_Cap_Ctrl0 Register; Table 15-7. Cmp_Cap_Ctrl0 Register Definitions; Timer 0 Compare/Capture Control Register (Cmp_Cap_Ctrl0) - Sharp LH79524 User Manual

Timers
15.2.2.2 Timer 0 Compare/Capture Control Register
(CMP_CAP_CTRL0)
CMP_CAP_CTRL0 allows programming the operating modes of Timer 0.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS NAME
31:16
15
14
13:12 CMP1
15-8

Table 15-6. CMP_CAP_CTRL0 Register

31 30 29 28 27
0 0 0 0
RO RO RO RO RO
15 14 13 12 11
PWM TC CMP1
0 0 0 0
RW RW RW RW RW

Table 15-7. CMP_CAP_CTRL0 Register Definitions

Reserved Reading this field returns 0. Write the reset value.
///
PWM Output Allows CTCMP0A to be used as a PWM output. This is done by
configuring this bit as well as other bits in this register. Refer to Section 15.1.3
for a complete explanation.
PWM
1 = Output pin CTCMP0A is in PWM Mode
0 = Output pin CTCMP0A is in Normal Mode and only uses the CMP0 Register
Timer 0 Counter Operation Programs Timer 0 as a free running counter or
as an interval timer. When 1, the counter clears upon matching the T0CMP1
Register. Refer to Section 15.1.1 for a complete explanation.
TC
1 = Clears counter when CNT0 for Timer 0 and T0CMP1 for Timer 0 match
0 = Inhibits counter clear (operates as free running counter)
Output Value Select Timer/Counter Operation: Programs the value (when a
compare match occurs) output on the CTCMP0B pin when the CNT0 Register
matches T0CMP1.
00 = No change occurs to CTCMP0B
01 = Output 0 to CTCMP0B
10 = Output 1 to CTCMP0B
11 = Toggle the output to CTCMP0B
PWM Operation:
00 = Invalid
01 = Active HIGH PWM output polarity
10 = Active LOW PWM output polarity
11 = Invalid
IMPORTANT: CMP1 and CMP0 must be programmed to the same polarity.
26 25 24 23
///
0 0 0 0 0
RO RO RO RO
10 9 8 7
CMP0 CAPE CAPD
0 0 0 0 0
RW RW RW RW
0xFFFC4000 + 0x04
DESCRIPTION
Version 1.0
LH79524/LH79525 User's Guide
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
CAPC CAPB
0 0 0 0 0
RW RW RW RW RW
17 16
0 0
RO RO
1 0
CAPA
0 0
RW RW