Cisco D9824 Installation And Configuration Manual page 137

Menu Item
Primary
Boot/Secondary
Boot
FPPIC
FPGA Safe
FPGA Current
Ver Register
CPLD Primary,
CPLD Secondary
Application, Select,
Erase
FPGA Version,
Select, Erase
78-4039426-01 Rev D
Description
Indicates the versions of the primary and secondary
processors' boot code.
Indicates the version of the front panel PIC microcontroller.
Indicates the version of the factory loaded safe Field
Programmable Gate Array (FPGA) code.
Indicates the version of the current Field Programmable Gate
Array (FPGA) code.
Indicates the version of FPGA code read from the FPGA.
Indicates the versions of the current primary and secondary
Complex Programmable Logic Device (CPLD).
Application - Select between all versions of the application
loaded on the current unit.
Select - Select and then scroll to Yes to reboot the unit and load
the selected application. You will be prompted to continue or
abort this operation.
Note: Selecting an application will cause the unit to reboot
and interrupt service.
Erase - Select to erase the selected application. You will be
prompted continue or abort this operation. You cannot erase
the safe application or the current application. While an
application is being erased, the busy indicator will appear.
You cannot earse another application until it is complete.
FPGA Version - Select between all versions of the FPGA code
loaded on the current unit.
Select - Select and then scroll to Yes to reboot the unit and load
the selected FPGA code. You will be prompted to continue or
abort this operation.
Note: Selecting an FPGA code will cause the unit to reboot
and interrupt service.
Erase - Select to erase the selected FPGA code. You will be
prompted continue or abort this operation. You cannot erase
the safe FPGA code or the current FPGA code. While an FPGA
code is being erased, the busy indicator will appear. You
cannot earse another FPGA code until it is complete.
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