In operating mode, operation of the on-chip clock pulse generator, CS0 area bus width
specification, power-down mode transition, and operation of the on-chip cache memory are
controlled.
3.1
Operating Mode of the On-chip Clock Pulse Generator
3.1.1
Clock Pulse Generator
The block diagram of the on-chip clock pulse generator is shown in figure 3.1.
Section 3 Operating Mode
Figure 3.1 Block Diagram of Clock Pulse Generator
Hitachi 47