Ccop Count Register (Ccnt); Input Counter (Ic[7:0])—Ccnt Bits 7–0; Run Counter (Rc[7:0])—Ccnt Bits 15–8; Figure 14-4 Ccop Count Register (Ccnt) - Motorola DSP56305 User Manual

On the cycle when the Input Counter reaches zero, CFSR input is disabled and the next
algorithm phase starts, driven by the Run Counter of the CCNT (RC[7:0], CCNT bits
8–15).
When CCOP is in the output phase, CDFR operates as an output data FIFO, i.e. it stores
the output data resulted by the CCOP processing and expects the DSP56300 core to read
it. Output data words are also generated and stored into the CDFR LSB first. CDFR is
accessible via core or DMA. The FIFO state machine is reset to its initial state by
hardware, software or CCOP individual reset.
14.4.2

CCOP Count Register (CCNT)

The CCOP Count Register (CCNT) is a 24-bit read/write register which holds the Input
Counter, Run Counter, and Output Counters. CCNT should be written at initialization
to set up the above counters, according to the algorithm to be processed by CCOP. The
CCNT bits are shown in Figure 14-4 and are described in the following paragraphs.
11
RC3 RC2 RC1 RC0 IC7
23
CM OC6 OC5 OC4 OC3 OC2 OC1 OC0 RC7 RC6 RC5 RC4
14.4.2.1 Input Counter (IC[7:0])—CCNT Bits 7–0
The Input Counter (IC[7:0]) is the first byte of the CCNT register. It specifies how many
bits in the CDFR are to be input into the CFSRs (the range is 0 to 120). After loading the
input data into the CDFR, the user should load this counter with the number of valid bits
to be shifted (one bit at a time) into the CFSRs. Starting on the following cycle, the Input
Counter decrements itself each cycle until it reaches zero. Each cycle that the Input
Counter is non-zero, the clock for the shift register is enabled causing a new bit to be
input to the CFSRs. The Input Counter is valid if CM (CCNT bit 23) is cleared, and
ignored if it is set.
14.4.2.2 Run Counter (RC[7:0])—CCNT Bits 15–8
The Run Counter (RC[7:0]) is the middle byte of the CCNT register. It specifies how
many cycles the CFSRs are to be shifted for the run phase, without any new data being
input (i.e. the data in the CFSRs will be modified only by the action of the feedback taps
MOTOROLA
10 9 8 7
22 21 20 19

Figure 14-4 CCOP Count Register (CCNT)

DSP56305 User's Manual
CYCLIC CODE CO-PROCESSOR
6 5 4 3
IC6 IC5 IC4 IC3
18 17 16 15
CCOP Programming Model
2 1 0
IC2 IC1 IC0
14 13 12
AA1303
14-9