Host Semaphores (Hs2-Hs0) Bits 16 And 14; Target Wait State Disable (Twsd) Bit 19 - Motorola DSP56305 User Manual

HOST INTERFACE (HI32)
HOST SIDE Programming Model
To assure proper operation, HRF1-HRF0 may be changed only if the DSP-to-host slave
data path is empty. In addition, switching between 32-bit data modes and non-32-bit
data modes may be done only in the personal software reset state (HM = $0 and HACT =
0).
The personal hardware reset clears HRF1-HRF0.
6.6.1.8

Host Semaphores (HS2-HS0) Bits 16 and 14

The HS2-HS0 bits may be used by the host processors for software arbitration of
mastership over the HI32. These bits do not affect the HI32 operation and only serve as a
read/write semaphore repository. These bits may be used as a mailbox between the
external hosts. For example: the semaphores may be used to assist HI32 bus arbitration
among several external hosts.
All external host processors that compete for mastership over the HI32 should work
according to the same software protocol for handling over the HI32 from one host
processor to another.
The personal hardware reset clears HS2-HS0.
6.6.1.9

Target Wait State Disable (TWSD) Bit 19

The TWSD bit is used to disable PCI wait states (which are inserted by negating
HTRDY), during a data phase.
If TWSD is cleared and the HI32 is in the PCI mode (HM=$1):
• the HI32 as the selected target in a read data phase from the HRXS, will insert PCI
wait states if the HRXS is empty (HRRQ = 0). Wait states will be inserted until the
data is transferred from the DSP side to the HRXS. Up to eight wait states may be
inserted before a target initiated transaction termination (disconnect-C/Retry)
will be generated.
• the HI32 as the selected target in a write data phase to the HTXR, will insert PCI
wait states if the HTXR is full (HTRQ = 0). Wait states will be inserted until the
data is transferred from the HTXR to the DSP side. Up to eight wait states may be
inserted before a target initiated transaction termination (disconnect-C/Retry)
will be generated.
• the HI32 as the selected target in a write data phase to the HCVR, will insert PCI
wait states if a host command is pending (HC = 1). Wait states will be inserted
until the pending host command is serviced. Up to eight wait states may be
inserted before a target initiated transaction termination (disconnect-C/Retry)
will be generated.
If TWSD is set and the HI32 is in the PCI mode (HM=$1):
6-64 DSP56305 User's Manual MOTOROLA