Motorola DSP56305 User Manual page 572

Equates
M_DCTR EQU $FFFFC5
; Host Control Register Bit Flags
M_HCIE EQU 0
M_STIE EQU 1
M_SRIE EQU 2
M_HF35 EQU $38
M_HF3 EQU 3
M_HF4 EQU 4
M_HF5 EQU 5
M_HINT EQU 6
M_HDSM EQU 13
M_HRWP EQU 14
M_HTAP EQU 15
M_HDRP EQU 16
M_HRSP EQU 17
M_HIRP EQU 18
M_HIRC EQU 19
M_HM0 EQU 20
M_HM1 EQU 21
M_HM2 EQU 22
M_HM EQU $700000
; Host PCI Control Register Bit Flags
M_PMTIE EQU 1
M_PMRIE EQU 2
M_PMAIE EQU 4
M_PPEIE EQU 5
M_PTAIE EQU 7
M_PTTIE EQU 9
M_PTCIE EQU 12
M_CLRT EQU 14
M_MTT EQU 15
M_SERF EQU 16
M_MACE EQU 18
M_MWSD EQU 19
M_RBLE EQU 20
M_IAE EQU 21
; Host PCI Master Control Register Bit Flags
M_ARH EQU $00ffff
M_BL EQU $3f0000
M_FC EQU $c00000
; Host PCI Address Register Bit Flags
M_ARL EQU $00ffff
M_C EQU $0f0000
B-4
; DSP CONTROL REGISTER (DCTR)
; Host Command Interrupt Enable
; Slave Transmit Interrupt Enable
; Slave Receive Interrupt Enable
; Host Flags 5-3 Mask
; Host Flag 3
; Host Flag 4
; Host Flag 5
; Host Interrupt A
; Host Data Strobe Mode
; Host RD/WR Polarity
; Host Transfer Acknowledge Polarity
; Host Dma Request Polarity
; Host Reset Polarity
; Host Interrupt
; Host Interrupt Request Control
; Host Interface Mode
; Host Interface Mode
; Host Interface Mode
; Host Interface Mode Mask
; PCI Master Transmit
; PCI Master Receive
; PCI Master Address
; PCI Parity Error
; PCI Transacton Abort Interrupt Enable
; PCI Transaction Term Interrupt Enable
; PCI Transfer Complet Interrupt Enable
; Clear Transmitter
; Master Transfer Terminate
; HSERR~ Force
; Master Access Counter Enable
; Master Wait States Disable
; Receive Buffer Lock Enable
; Insert Address Enable
; DSP PCI Transaction Address (High)
; PCI Data Burst Length
; Data Transfer Format Control
; DSP PCI Transaction Address (Low)
; PCI Bus Command
DSP56305 User's Manual
Request Polarity
Interrupt Enable
Interrupt Enable
Interrupt Enable
Interrupt Enable
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