Dsp56305 Core Description; General Features; Hardware Debugging Support; Reduced Power Dissipation - Motorola DSP56305 User Manual

1.5

DSP56305 CORE DESCRIPTION

Core features are described fully in the
peripheral features are described in this manual.
1.5.1

General Features

• 80 Million Instructions Per Second (MIPS) with an 80 MHz clock at 3.3 V
• Object code compatible with the DSP56000 core
• Highly parallel instruction set
1.5.2

Hardware Debugging Support

• On-Chip Emulation (OnCE) module
• Joint Action Test Group (JTAG) Test Access Port (TAP)
• Address Tracing mode reflects internal accesses at the external port
1.5.3

Reduced Power Dissipation

• Very low power CMOS design
• Wait and Stop low power standby modes
• Fully-static logic, operation frequency down to 0 Hz (dc)
• Optimized power management circuitry (instruction-dependent,
peripheral-dependent, and mode-dependent)
MOTOROLA
DSP56300 Family Manual
DSP56305 User's Manual
DSP56305 Overview
DSP56305 Core Description
. Pinout, memory, and
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