Table 5-1 Example For Cycle Count With Cache Enabled Versus Disabled - Motorola DSP56600 Manual

Instruction Cache and Memory Features
The Instruction Cache
5-2 Optimizing DSP56300/DSP56600 Applications
Activating the cache requires only setting the CE bit in the SR. The
following instruction activates the cache:
Because of pipelining, allow four instructions to execute before
assuming the cache is active. Disabling the cache is done by clearing
that bit.
Note: For obvious reasons, the user should not enable the cache
while running from the cacheable memory area itself.
To demonstrate the benefit of cache use, consider the example in
Table 5-1, taken from a benchmark for FIR lattice filter (the
DSP56300 Family Manual , Appendix C).
Table 5-1 Example for Cycle Count with Cache Enabled Versus
Program Code
movep x:IN,b
move
move
do
macr x0,y0,b
tfr x0,a
macr y1,y0,a
_END
movep b,x:OUT
move
In the example, each external fetch inserts 3 wait states. Therefore,
the execute time needed for each instruction in the loop is 4 cycles: 1
cycle for execution, and 3 wait states for the instruction that is being
fetched in parallel. In other words, due to the pipelining, the wait
states of an instruction stalls the execution of the instruction
bset #19,SR
Disabled
x:(r0)+,x0 y:(r4)+,y0
b,a
#N,_END
b,y1
x:(r0)+
x:(r0),x0 y:(r4)+,y0
a,x:(r0)+ y:(r4)-,y0
External
Program Hit
Words Cycles
Cycles
1 1
1 1
1 1
2 5
1 1
1 1
1 1
1 1
1 1
Total: 3N+10 12N+31
MOTOROLA
Miss
4
4
4
11
4
4
4
4
4