Memory Space Enable (Mse) Bit 1; Bus Master Enable (Bm) Bit 2; Parity Error Response (Perr) Bit 6; Wait Cycle Control (Wcc) Bit 7 - Motorola DSP56305 User Manual

HOST INTERFACE (HI32)
HOST SIDE Programming Model
The CSTR/CCMR is a PCI standard 32-bit read/write register mapped into the PCI
configuration space, when in the PCI mode or in mode 0 (HM=$1 or $0). CSTR/CCMR is
accessed if a configuration read/write command is in progress and the PCI address is
$04. In the Self Configuration mode (HM = $5): the DSP56300 core can indirectly access
the CCMR. (see Section 6.7)
The CSTR/CCMR is written by the host in accordance with the byte enables. Byte lanes
that are not enabled are not written and the corresponding bits remain unchanged.
The CSTR/CCMR cannot be accessed by the host when not in the PCI mode (HM≠$1).
The CSTR/CCMR bits are described in the following paragraphs.
6.6.8.1

Memory Space Enable (MSE) Bit 1

The MSE bit is used to control the HI32 response to the PCI memory space accesses,
when in the PCI mode (HM=$1). The HI32 memory space response is disabled if MSE is
cleared and enabled if MSE is set.
The personal hardware reset clears MSE.
6.6.8.2

Bus Master Enable (BM) Bit 2

The BM bit is used to control the HI32 ability to act as a master on the PCI bus, when in
the PCI mode (HM=$1). If BM is cleared, the HI32 is disabled from acting as a bus
master. If BM is set, the HI32 can function as a bus master. This bit affects the MARQ bit
in the DSP side status register (DPSR): if BM is cleared, MARQ is also cleared.
The personal hardware reset clears BM.
6.6.8.3

Parity Error Response (PERR) Bit 6

The PERR bit is used to control the HI32 response to parity errors, when in the PCI mode
(HM=$1). If PERR is cleared: the HI32 does not drive HPERR. If PERR is set: if a parity
error is detected the HI32 pulses the HPERR signal. If a parity error or HPERR low is
detected, the HI32 sets the DPR bit in the CSTR/CCMR
In both cases the HI32 sets bit 15 (DPE) in the CSTR/CCMR, sets DPER in the DPSR, and
generates a parity error interrupt request if PEIE, in the DPCR, is set.
The personal hardware reset clears PERE.
6.6.8.4

Wait Cycle Control (WCC) Bit 7

The WCC bit is hardwired to zero, as the HI32 never executes address stepping.
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