On-Chip Memory; Table 1-2 On Chip Memory - Motorola DSP56305 User Manual

DSP56305 Overview
DSP56300 Core Functional Blocks
The test logic includes a TAP consisting of four dedicated signals, a 16-state controller,
and three test data registers. A boundary scan register links all device signals into a
single shift register. The test logic, implemented utilizing static logic design, is
independent of the device system logic. More information on the JTAG port is provided
in
Section 11, JTAG Port.
The On-Chip Emulation (OnCE) module provides a means of interacting with the
DSP56300 core and its peripherals non-intrusively so that a user can examine registers,
memory, or on-chip peripherals. This facilitates hardware and software development on
the DSP56300 core processor. OnCE module functions are provided through the JTAG
TAP signals. More information on the OnCE module is provided in
Emulation Module.
1.6.6

On-Chip Memory

The memory space of the DSP56300 core is partitioned into program memory space, X
data memory space, and Y data memory space. The data memory space is divided into X
data memory and to Y data memory in order to work with the two Address ALUs and to
feed two operands simultaneously to the Data ALU. Memory space includes internal
RAM and ROM and can be expanded off-chip under software control. More information
on the internal memory is provided in
Program RAM, Instruction Cache, X data RAM, and Y data RAM size are programmable
as described in Table 1-2, On Chip Memory, below:
Instruction Switch
Cache Mode
disabled disabled
enabled disabled
disabled enabled
enabled enabled
There are on-chip ROMs for program memory (6 K x 24-bit), bootstrap memory (192
words x 24-bit), and Y data memory (3 K x 24-bit).
1-12
Section 3, Memory Configuration

Table 1-2 On Chip Memory

Program RAM Instruction
Size Cache Size
6.5 K × 24-bit
5.5 K × 24-bit 1 K × 24-bit
7.5 K × 24-bit
6.5 K × 24-bit 1 K × 24-bit
DSP56305 User's Manual
Section 10, On-Chip
X Data RAM
Size
3.75 K × 24-bit
0
3.75 K × 24-bit
2.75 K × 24-bit
0
2.75 K × 24-bit
.
Y Data RAM
Size
2 K × 24-bit
2 K × 24-bit
2 K× 24-bit
2 K × 24-bit
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