Gsm Fire Decode - Motorola DSP56305 User Manual

CYCLIC CODE CO-PROCESSOR
Configuration Examples
14.7.3

GSM Fire Decode

The Fire decode processes the data block plus the CRC sequence calculated by the Fire
encode. Fire decode is capable of correcting any burst of errors up to 12 bits in length.
The algorithm makes use of the generator polynomial G(D) as well as a multiplication
polynomial M(D) given by:
( )
M D
The Fire decode flow is composed of the following steps:
1. Invert the received 40 CRC bits. This is done by the core and is based on the
assumption that the CRC bits were inverted prior to transmission.
2. Set Input Counter = 224, and Run Counter = 224 (in CCNT)
3. Set INE0 and INE1 in CSFTB
4. Set OPM[1:0], HOZD, and clear LRC (in CCSR)
5. Insert 224 bits (184 data bits + 40 inverted CRC) - CCOP input phase.
6. If D1 to D40 (the 40 MSB's of the concatenated CFSR) equal zero, then the data
block is error free. Terminate processing.
7. Otherwise, an error is present, enter run phase and:
a. Shift CFSR (input data disabled) until D1 - D28 equals zero.
The start location of the burst error is the number of shifts done until D1– D28
equal zero. This is determined by 224 minus the Run Counter value after a
zero is detected in bits D1–D28.
b. If the start location lies in the data sequence (bits 0 – 183), the errors are
corrected by XORing the data bits with the contents of D40 – D29.
The 12-bit correcting sequence is determined by reading CFSRA and
extracting the bits D40 – D29 (bits 19:8 in CFSRA).
c. If the number of shifts exceeds 224 without D1 – D28 = 0 detection, data is
uncorrectable. This is determined by process termination (PCDN set) while
Run Counter equals zero (224 shifts done).
The CFSR configuration for GSM Fire decode is shown in Figure 14-11.
14-30
39 33 29
= D + D + D
DSP56305 User's Manual
27 16 10
+ D + D + D +
6 4
D + D + 1
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