Introduction To The Timer/Event Counter; Timer/Event Counter Architecture - Motorola DSP56305 User Manual

9.1

INTRODUCTION TO THE TIMER/EVENT COUNTER

This section describes the internal Timer/Event Counter module (TEC) in the DSP56305.
The TEC comprises:
• a 21-bit prescaler counter
• a 24-bit Timer Prescaler Load Register (TPLR)
• a 24-bit Timer Prescaler Count Register (TPCR)
• three identical independent general purpose 24-bit timer/event counters, each
having its own register set
Each timer/event counter comprises:
• a 24-bit counter
• a 24-bit read/write Timer Control and Status Register (TCSR)
• a 24-bit write-only Timer Load Register (TLR)
• a 24-bit read/write Timer Compare Register (TCPR)
• a 24-bit read-only Timer Count Register (TCR)
• logic for clock selection and interrupt/DMA trigger generation
Figure 9-1 shows the TEC block diagram. Figure 9-2 shows the TEC programming
model. Figure 9-5 shows the generic timer block diagram. Figure 9-6 shows the generic
timer programming model.
9.2

TIMER/EVENT COUNTER ARCHITECTURE

The following sections details the TEC architecture's component parts.
MOTOROLA
Introduction to the Timer/Event Counter
DSP56305 User's Manual
Timer/Event Counter
9-3