Transmitter Ready (Trdy) Bit 0; Host Transmit Data Request (Htrq) Bit 1 - Motorola DSP56305 User Manual

6.6.2.1

Transmitter Ready (TRDY) Bit 0

The TRDY status bit indicates that both the HTXR and the DRXR registers are empty. If
TRDY is set to one, the data that the host processor writes to the HTXR will be
immediately transferred to the DSP side of the HI32. This has many applications. For
example: if the host processor issues a host command which causes the DSP56300 core to
read the DRXR, the host processor can be guaranteed that the data it just transferred to
the HI32 is what is being received by the DSP56300 core.
In order to support high speed data transfers, the HI32 host-to-DSP data path is a six
word deep FIFO (five word deep in the Universal Bus modes, three word deep in the
32-bit mode, HM = $1 and HTF = $0). In PCI data transfers with HM = $1 and HTFπ$0, if
TRDY is set, the HI32 will not insert wait states in the next six data transfers written by
the host to the HTXR. In PCI data transfers with HM = $1 and HTF = $0 (i.e. 32-bit
mode), if TRDY is set, the HI32 will not insert wait states in the next three data phases
written by the host to the HTXR. In Universal bus mode data transfers, if TRDY is set, the
HI32 will not insert wait states in the next five data transfers written by the host to the
HTXR.
TRDY is cleared when the HTXR is written by the host processor.
Hardware, software and personal software resets set TRDY.
6.6.2.2

Host Transmit Data Request (HTRQ) Bit 1

The HTRQ bit indicates that the host transmit data FIFO (HTXR) is not full and can be
written by the host processor. HTRQ is set when the HTXR data is transferred to the
DRXR. HTRQ is cleared when the HTXR is filled by host processor writes.
In the PCI mode:
The HI32 as target in a write data phase to the HTXR, will deassert HTRDY, and insert
up to eight PCI wait cycles, if HTRQ is cleared.
In a Universal Bus mode write to the HTXR, the HI32 slave will deassert HTA as long as
HTRQ is cleared. HTRQ may be used to assert the external HIRQ signal if the TREQ bit is
set. Regardless of whether the HTRQ host interrupt request is enabled, HTRQ provides
valid status so that polling techniques may be used by the host processor.
Hardware, software and personal software resets set HTRQ.
MOTOROLA DSP56305 User's Manual
HOST INTERFACE (HI32)
HOST SIDE Programming Model
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