Motorola DSP56305 User Manual page 227

Bit
1
2
6
7
8
9,5-3, 0 not
15-10
23
24
26-25
27
28
29
30
31
22-16
MOTOROLA
Name
MSE Memory Space Enable
BM Bus Master Enable
PERR Parity Error Response
WCC Wait Cycle Control (hardwired to zero)
SERE System Error Enable
implemented
reserved
FBBC Fast Back-to-Back Capable (hardwired to
one)
DPR Data Parity Reported
DST1-DST0 DEVSEL Timing (hardwired to $1)
STA Signaled Target Abort
RTA Received Target Abort
RMA Received Master Abort
SSE Signaled System Error
DPE Detected Parity Error
reserved
DSP56305 User's Manual
HOST INTERFACE (HI32)
HOST SIDE Programming Model
Function
6-79