Motorola DSP56305 User Manual page 225

The HTXR receives data from the HI32 data signals via the data transfer format
converter (HDTFC). The value of the FC bits in the HCTR or the HTF bits in the HCTR
define which bytes of the PCI bus are written to the HTXR and their alignment. (See
Table 6-5, Section 6.5.7, and Table 6-15).
In the PCI mode (HM = $1):
As the active target, in a memory space write transaction, the HTXR is accessed if the
PCI address is between HI32_base_address: $01C and HI32_base_address: $FFFC (i.e.
the HTXR is viewed by the host processor as a 16377 Dword write-only memory).
As the active master, all data read from the target being accessed is written to the HTXR.
In PCI host-to-DSP data transfers, data is written to the HTXR FIFO, in accordance with
FC1-FC0 or HTF1-HTF0 bits, regardless of the value of the byte enable signals
(HC3/HBE3-HC0/HBE0).
In a Universal Bus mode (HM=$2 or $3), the HTXR is accessed if the HA10-HA3 value
matches the HI32 base address (CBMA, see Section 6.6.11) and the HA2-HA0 value is $7.
In a 24-bit data Universal Bus mode (HM=$2 or $3 and HTF = $0), the HTXR is viewed
by the host processor as a 24-bit write-only register. HD23-HD0 signals are written to all
three bytes of the HTXR in a write access.
In a 16-bit data Universal Bus mode (HM=$2 or $3 and HTF≠$0), the HTXR is viewed by
the host processor as a 16-bit write-only register. In a write access, the HD15-HD0
signals are written to the two most significant bytes or least significant bytes of the
HTXR, as defined by the HTF bits in the HCTR.
When HTRQ is set and TREQ in the HCTR is set:
• the HREQ status bit will be set in the HSTR.
• the HIRQ signal will be asserted - if DMAE is cleared (in the Universal Bus
modes)
• the HDRQ signal will be asserted - if DMAE is set (in the Universal Bus modes)
If TWSD is cleared, the HI32 as the selected PCI target (HM=$1) in a write data phase to
the HTXR will insert PCI wait states if the HTXR is full (HTRQ = 0). Wait states will be
inserted until the data is transferred from the HTXR to the DSP side. Up to eight wait
states may be inserted before a target initiated transaction termination
(disconnect-C/Retry) will be generated.
In a Universal Bus mode write to the HTXR the HI32 will insert wait states if the HTXR is
full (HTRQ = 0). Wait states will be inserted until the data is transferred from the HTXR
to the DSP side.
Hardware, software and personal software resets empty the HTXR (HTRQ is set).
MOTOROLA DSP56305 User's Manual
HOST INTERFACE (HI32)
HOST SIDE Programming Model
6-77