Motorola DSP56305 User Manual page 306

Enhanced Synchronous Serial Interface (ESSI)
Operating Modes
Time slots are contiguous – with one exception, the last bit time in time slot K is always
immediately followed by the first bit time in time slot K+1. The exception involves the
last time slot in the frame, in conjunction with an external frame sync. If an internal frame
sync is used, the last time slot in the frame will be contiguous with the first time slot in
the next frame. The same situation is possible, but not required, if an external frame sync
is used. In summary, it is possible for an ESSI receive or transmit channel to transfer a
new data bit during every bit time in the frame.
Each ESSI in the network is assigned zero, one, or more receive time slots, and zero, one,
or more transmit time slots. The time slot assignment scheme used is dependent on the
network topology and software multiprocessing algorithm which is used. The receive
and transmit time slots of a given ESSI may be assigned independently of each other if
its receive and transmit pins are on different network nodes, and the multiprocessing
algorithm does not cause them to be interdependent.
An ESSI must receive or transmit only during its assigned receive or transmit time slots,
respectively. For the case in which transmitters from more than one ESSI are connected
to a given network node, this will prevent network collisions. The core code must also
take into account the inherent delays which occur in the ESSI due to double buffering
and serial/parallel conversion. Data written to the transmit register(s) in time slot K will
be shifted out of the ESSI in time slot K+1; data read from the receive register in time slot
K was shifted into the ESSI in time slot K-1. For the purposes of this discussion, any
reference to a "time slot" is from the core point of view. In other words, this is the time
slot in which the appropriate ESSI data register is read or written, as opposed to when
the serial data is actually transferred.
Time slot mask registers may be used to constrain an ESSI to transferring data only
during its assigned time slots. These registers are used to disable the receiver or
transmitter(s), along with the associated status flags, during all but the assigned time
slots. The result is that actions triggered by an ESSI's status flags or interrupts will only
occur during that ESSI's designated receive or transmit time slots. Masking out
unneeded time slots saves core MIPS because the ISRs are only called during the
assigned time slots. Time slot assignment may be predesignated or changed dynamically
(mask register changes take effect in the following frame).
If an ESSI needs to receive during more than one time slot per frame, or transmit during
more than one time slot per frame, then a system must be employed for tracking the
assigned slots within a given frame. Various solutions are possible, such as multiple
DMA channels, software counters, or input/output buffers with a known data
interleaving scheme.
Details on programming the ESSI in network mode are given in subsequent sections.
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