Motorola DSP56305 User Manual page 22

13.5.3.6 Flush Enable (FLEN)-VCRA Bit 5 . . . . . . . . . . . . . . . 13-19
13.5.3.7 Code Rate (RATE[1:0])-VCRA Bits 8-9. . . . . . . . . . . 13-20
13.5.3.8 Constraint Length (CNST[1:0])-VCRA Bit 12-13 . . . . 13-20
13.5.3.9 VCRA Reserved-VCRA Bits 6-7, 10-11, 14-15 . . . . 13-20
13.5.4 Viterbi Control Register B (VCRB) . . . . . . . . . . . . . . . . . . 13-21
13.5.4.1 Initial State Enable (ISE)-VCRB Bit 0. . . . . . . . . . . . . 13-21
13.5.4.2 Flush Control (FLC)-VCRB Bit 1 . . . . . . . . . . . . . . . . 13-21
13.5.4.3 Continuous Mode Enable (CME)-VCRB Bit 3 . . . . . . 13-21
13.5.4.4 Data Mode (HD[0])-VCRB Bits 4-5 . . . . . . . . . . . . . . 13-22
13.5.4.5 Window Error Detection Enable (WEDE)-VCRB Bit 6 13-22
13.5.4.6 Data-In Interrupt Enable (DIIE)-VCRB Bit 8 . . . . . . . . 13-22
13.5.4.7 Buffer Full Interrupt Enable (BFIE)-VCRB Bit 10 . . . . 13-22
13.5.4.8 Data Out Interrupt Enable (DOIE)-VCRB Bit 11. . . . . 13-22
13.5.4.9 Processing Done Interrupt Enable (DNIE)-
VCRB Bit 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-22
13.5.4.10 Operation Complete Interrupt Enable (OCIE)-
VCRB Bit 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-22
13.5.4.11 Reserved Bits-VCRB Bits 2, 5, 9, 14-15 . . . . . . . . . . 13-22
13.5.4.12 Internal Reserved Bits-VCRB Bits 4, 7. . . . . . . . . . . . 13-23
13.5.5 Viterbi Status Register (VSTR) . . . . . . . . . . . . . . . . . . . . . 13-23
13.5.5.1 Initialize Flag (INIT)-VSTR Bit 0 . . . . . . . . . . . . . . . . . 13-23
13.5.5.2 Flush Flag (FLSH)-VSTR Bit 1. . . . . . . . . . . . . . . . . . 13-23
13.5.5.3 Operation Complete (OPC)-VSTR Bit 4. . . . . . . . . . . 13-23
13.5.5.4 Processing Done (DONE)-VSTR Bit 5 . . . . . . . . . . . . 13-24
13.5.5.5 Data Ready (DRDY)-VSTR Bit 6 . . . . . . . . . . . . . . . . 13-24
13.5.5.6 End Stage (ESTG)-VSTR Bit 7 . . . . . . . . . . . . . . . . . 13-24
13.5.5.7 Data Request (DREQ)-VSTR Bit 8 . . . . . . . . . . . . . . 13-24
13.5.5.8 Data Output Buffer Full (DOBF)-VSTR Bit 9 . . . . . . . 13-24
13.5.5.9 Reserved Bits-VSTR Bits 2, 3, 10-15 . . . . . . . . . . . . 13-24
13.5.6 Viterbi Data Counter (VCNT) . . . . . . . . . . . . . . . . . . . . . . 13-25
13.5.7 Viterbi Tap A Register (VTPA) . . . . . . . . . . . . . . . . . . . . . 13-25
13.5.7.1 Tap Vector A (TAPA{4:0])-VTPA Bits 4-0 . . . . . . . . . 13-25
13.5.7.2 Tap Vector B (TAPB[4:0])-VTPA Bits 9-5 . . . . . . . . . 13-25
13.5.7.3 Tap Vector C (TAPC[4:0])-VTPA Bits 14-10 . . . . . . . 13-25
13.5.7.4 Reserved Bit-VTPA Bit 15 . . . . . . . . . . . . . . . . . . . . . 13-25
13.5.8 Viterbi Tap Register B (VTPB) . . . . . . . . . . . . . . . . . . . . . 13-26
xx DSP56305 User's Manual MOTOROLA