Table 2-9 Interrupt And Mode Control - Motorola DSP56305 User Manual

Signal/Connection Descriptions
Interrupt and Mode Control
Signal
Type
Name
RESET Input
MODA Input
IRQA Input
2-16

Table 2-9 Interrupt and Mode Control

State
During
Reset
Input Reset—RESET is an active-low, Schmitt-trigger input.
Deassertion of RESET is internally synchronized to the clock
out (CLKOUT). When asserted, the chip is placed in the Reset
state and the internal phase generator is reset. The
Schmitt-trigger input allows a slowly rising input (such as a
capacitor charging) to reset the chip reliably. If RESET is
deasserted synchronous to CLKOUT, exact start-up timing is
guaranteed, allowing multiple processors to start
synchronously and operate together in "lock-step." When the
RESET signal is deasserted, the initial chip operating mode is
latched from the MODA, MODB, MODC, and MODD inputs.
The RESET signal must be asserted after power up.
This input is 5 V tolerant.
Input Mode Select A—MODA selects the initial chip operating
mode during hardware reset and becomes a level-sensitive or
negative-edge-triggered, maskable interrupt request input
IRQA during normal instruction processing. MODA, MODB,
MODC, and MODD select one of sixteen initial chip operating
modes, latched into the OMR when the RESET signal is
deasserted.
External Interrupt Request A—IRQA is an active-low
Schmitt-trigger input, internally synchronized to CLKOUT. If
IRQA is asserted synchronous to CLKOUT, multiple
processors can be re-synchronized using the WAIT instruction
and asserting IRQA to exit the Wait state. If the processor is in
the Stop standby state and IRQA is asserted, the processor will
exit the Stop state.
These inputs are 5 V tolerant.
DSP56305 User's Manual
Signal Description
MOTOROLA