Table 6-13 Hirq And Hdrq Signal Definition; Receive Request Enable (Rreq) Bit 2 - Motorola DSP56305 User Manual

HOST INTERFACE (HI32)
HOST SIDE Programming Model
6.6.1.2

Receive Request Enable (RREQ) Bit 2

The RREQ bit is used to control the HIRQ and HDRQ signals for DSP-to-host data
transfers (see Table 6-13), when in a Universal Bus mode (HM=$2 or $3).
If DMAE is cleared, RREQ enables the host interrupt request (HIRQ) signal when the
host receive data request (HRRQ) status bit in the HSTR is set. If RREQ is cleared, HRRQ
host interrupt requests are disabled. If RREQ is set, the host interrupt request HIRQ
signal will be asserted if HRRQ is set. HDRQ is deasserted.
If DMAE is set, RREQ enables the host DMA request (HDRQ) signal when the host
receive data request (HRRQ) status bit in the HSTR is set. If RREQ is cleared, HRRQ host
DMA requests are disabled. If RREQ is set, the host DMA request HDRQ signal will be
asserted if HRRQ is set. HIRQ is deasserted (high impedance if HIRD = 0 in the DCTR).
The personal hardware reset clears RREQ.
Note: In a Universal Bus mode (HM = $2 or $3), when both the TREQ and RREQ
control bits (in the HCTR) are cleared, host interrupt request / strobe /
acknowledge hardware handshake (using the HIRQ / Data Strobe / HTA
signals) is disabled. The host may poll the HTRQ, HRRQ status bits or use the
host data strobe/acknowledge hardware handshake (using the
Data Strobe / HTA signals) (see Table 6-5).
DMAE TREQ RREQ
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
a. high impedance if HIRD = 0 in the DCTR
6-56

Table 6-13 HIRQ and HDRQ Signal Definition

HIRQ Signal
a
deasserted (HRRQ, HTRQ polling)
HRRQ Host Interrupt Requests
Enabled
HTRQ Host Interrupt Request Enabled high impedance
HRRQ, HTRQ Interrupt Requests
Enabled
a
deasserted
a
deasserted
a
deasserted
a
deasserted
DSP56305 User's Manual
HDRQ signal
high impedance
high impedance
high impedance
high impedance
HRRQ DMA Request Enabled
HTRQ DMA Request Enabled
HRRQ, HTRQ Host DMA Requests
Enabled
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