Host Command Vector Register (Hcvr) - Motorola DSP56305 User Manual

HOST INTERFACE (HI32)
HOST SIDE Programming Model
6.6.3

Host Command Vector Register (HCVR)

31 30 29 28
15 14 13 12
HNMI
Reserved, read as zero and should be written zero
Bit
7-1
15
31-16,14-8 reserved
The HCVR is a 32-bit read/write register used by the host processor to cause the
DSP56300 core to execute a vectored interrupt. The host command feature is
independent of any of the data transfer mechanisms in the HI32. It can be used to cause
any of the 128 possible interrupt routines in the DSP to be executed.
When the HCVR is read to the PCI bus (HM=$1), the HAD31-HAD0 signals are driven
with the HCVR data during a read access; and these signals are written to the HCVR in a
write access.
In a 24-bit data Universal Bus mode (HM=$2 or $3 and HTF = $0 or HRF = $0), the
HD23-HD0 signals are driven with the three least significant bytes of the HCVR in a read
access; HD23-HD0 are written to the three least significant bytes of the HCVR, the most
significant portion is zero filled during the HCVR write.
In a 16-bit data Universal Bus mode (HM=$2 or $3 and HTF≠$0 or HRF≠$0), the
HD15-HD0 signals are driven with the two least significant bytes of the HCVR in a read
access; HD15-HD0 are written to the two least significant bytes of the HCVR, the most
significant portion is zero filled during the HCVR write.
In PCI mode (HM = $1) memory space transactions, the HCVR is accessed if the PCI
address is HI32_base_address: $018.
6-72
27 26 25
11 10 9
Name
0 HC
HV6-HV0
HNMI
DSP56305 User's Manual
24 23 22 21
8 7 6 5
HV6 HV5 HV4
Function
Host Command
Host Command Vector
Host Non Maskable Interrupt
20 19 18 17
4 3 2 1
HV3 HV2 HV1 HV0
MOTOROLA
16
0
HC