Initialization; Normal Operation; Flush Operation; Figure 13-6 Viterbi Co-Processor In Equalization Mode - Motorola DSP56305 User Manual

PMB Interface
BM
VP RAM
32 × 16

Figure 13-6 Viterbi Co-Processor in Equalization Mode

13.4.1.1

Initialization

Enter the expected number of bits to equalize into VCNT, or select the continuous
operation mode by setting the CME bit (VCRB Bit 3).
13.4.1.2

Normal Operation

A 16-bit MF value is supplied to the VCOP. For every update-cycle, a pass over all trellis
states is performed. The survivor is found by the ACS block and a decoded bit is
delivered from the Trellis block. The equalized data is then moved to the output buffer
used for data transfers to the DSP56300 core processor. The equalized data can be read
one symbol-bit at a time, using a core interrupt or DMA transfer. When all the input data
have been processed, the VCOP flushes the data remaining in the trellis.
13.4.1.3

Flush Operation

In this stage, there are no more MF inputs and only the remaining bits in the trellis
memory are left to process. The trellis path is selected according to the Flush Control
mode (ending state or best metric), and the remaining bits are shifted out.
MOTOROLA
ACS
Metric RAM
64 × 22
WED
WED RAM
64 × 16
Rx Qual
Convolutional
Encoder
DSP56305 User's Manual
VITERBI CO-PROCESSOR
Trellis
Trellis RAM
64 × 36 × 1
Operating Modes
Data Control
Output Buff
63 × 16 bit /
1023 × 1 bit
AA1316
13-11