Watchdog Modes; Watchdog Pulse (Mode 9) - Motorola DSP56305 User Manual

equal to [($FFFFFF – TCPR) / ($FFFFFF − TLR + 1)]. For a 50% duty cycle, the TCPR
value is equal to ($FFFFFF + TLR + 1) / 2.
Note: The TCPR value must be greater than the TLR value.
9.4.4

Watchdog Modes

The following Watchdog Timer modes are provided:
• Watchdog Pulse
• Watchdog Toggle
9.4.4.1

Watchdog Pulse (Mode 9)

Bit Settings
TC3 TC2 TC1
1 0 0
In this mode, the timer generates an external signal at a preset rate. The signal period is
equal to the period of one timer clock.
Set the TE bit to clear the counter and enable the timer. The value the timer is to count is
loaded into the TCPR. The counter is loaded with the TLR value on the first timer clock
received from either the DSP56305 internal clock divided by two (CLK/2) or the
prescaler clock output. Each subsequent timer clock increments the counter.
When the counter matches the TCPR value, the TCF bit in the TCSR is set, and if the
TCIE bit is also set a compare interrupt is generated.
If the TRM bit is set, the counter is loaded with the TLR value on the next timer clock and
the count is resumed. If the TRM bit is cleared, the counter continues to be incremented
on each subsequent timer clock.
This process is repeated until the timer is disabled (i.e., TE is cleared).
If the counter overflows, the TOF bit is set; if TOIE is set, an overflow interrupt is
generated. At the same time, a pulse is output on the TIO signal with a pulse width equal
to the timer clock period. The pulse polarity is determined by the value of the INV bit. If
MOTOROLA
TC0 Mode Name
1 9 Pulse
DSP56305 User's Manual
Timer Modes of Operation
Mode Characteristics
Kind
Watchdog
Timer/Event Counter
TIO Clock
Output Internal
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