Interrupt And Mode Control - Motorola DSP56305 User Manual

Table 2-8 External Bus Control Signals (Continued)
Signal
Type
Name
BCLK Output
BCLK Output
2.7

INTERRUPT AND MODE CONTROL

The interrupt and mode control signals select the chip's operating mode as it comes out
of hardware reset. After RESET is deasserted, these inputs are hardware interrupt
request lines.
MOTOROLA
State During
Reset, Wait,
or Stop
Tri-stated Bus Clock—When the DSP is the bus master, BCLK is
an active-high output used by Synchronous Static
Random Access Memory (SSRAM) to sample address,
data, and control signals. BCLK is active either during
SSRAM accesses or as a sampling signal when the
program Address Tracing mode is enabled (by setting
the ATE bit in the OMR). When BCLK is active and
synchronized to CLKOUT by the internal PLL, BCLK
precedes CLKOUT by one-fourth of a clock cycle. The
BCLK rising edge may be used to sample the internal
Program Memory access on the A0–A23 address lines.
Tri-stated Bus Clock Not—When the DSP is the bus master,
BCLK is an active-low output that is the inverse of the
BCLK signal. When the DSP is not the bus master, the
signal is tri-stated.
DSP56305 User's Manual
Signal/Connection Descriptions
Interrupt and Mode Control
Signal Description
2-15