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13.4.6
VCOP Individual Reset State
The VCOP Individual Reset state is entered whenever the ME bit in VCRA is cleared. In
this state, status bits are cleared, internal pointers and internal circuits are reset to their
default values. Control bits are preserved.
13.4.7
Idle State
The Idle state is entered upon exiting the VCOP individual reset state, whenever the
VCOP operation is disabled (all of the bits MAEN, DECEN, ENCEN, EQEN, and FLEN
in VCRA are cleared) and at the end of processing a block of data. In this state, the VCOP
state machine is idle; clocks are enabled but internal pointers and internal circuits are
reset to their default values. Control bits and OPC status bit in VSTR are preserved,
while the remaining status bits in VSTR are cleared.
MOTOROLA
DSP56305 User's Manual
VITERBI CO-PROCESSOR
Operating Modes
13-15
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