Motorola DSP56305 User Manual page 250

Table 6-18 Host Port Signals - Detailed Description (Sheet 10 of 13)
HI32
Port
PCI
a
Pin
HIDSEL
Initialization Device Select
Input signal.
Used as a chip select in lieu of the
upper 21 address lines during
configuration read and write
transactions.
HFRAME
Cycle Frame
Sustained tri-state bidirectional
c
signal.
Driven By the current master to
indicate the beginning and duration
of an access. HFRAME is deasserted
in the final data phase of the
transaction.
HI32 Mode
Enhanced Universal
HRD/HDS
Host Read/Data Strobe
Schmitt trigger input signal.
When in the double-strobe mode of the HI32 (HDSM = 0),
this signal functions as the host read strobe (HRD). The
host processor initiates a read access by asserting HRD.
Data output may be latched with the rising edge of HRD.
When in the single-strobe mode of the HI32 (HDSM = 1),
this signal functions as the host data strobe (HDS). The
host processor initiates a read access by asserting HDS
with HRW asserted. Data output may be latched with the
rising edge of HDS. The host processor initiates a write
access by asserting HDS with HRW deasserted. Data input
is latched by the HI32 with the rising edge of HDS.
NOTE: The simultaneous assertion of HRD and HWR
is illegal.
UNUSED
Must be forced or pulled up to Vcc.
b
Universal
GPIO
Disconnected