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Signal/Connection Descriptions
Power
2.2
POWER
Power Name
(# of Pins)
V
PLL Power—V
CCP
The voltage should be well-regulated and the input should be provided
with an extremely low impedance path to the V
V
(4)
Quiet Power—V
CCQ
logic. This input must be tied externally to all other chip power inputs. The
user must provide adequate external decoupling capacitors.
V
(6)
Address Bus Power—V
CCA
address bus I/O drivers. This input must be tied externally to all other chip
power inputs. The user must provide adequate external decoupling
capacitors.
V
(4)
Data Bus Power—V
CCD
bus I/O drivers. This input must be tied externally to all other chip power
inputs. The user must provide adequate external decoupling capacitors.
V
(2)
Bus Control Power—V
CCN
drivers. This input must be tied externally to all other chip power inputs.
The user must provide adequate external decoupling capacitors.
V
(6)
Host Power—V
CCH
input must be tied externally to all other chip power inputs. The user must
provide adequate external decoupling capacitors.
V
(2)
ESSI, SCI, and Timer Power—V
CCS
SCI, and timer I/O drivers. This input must be tied externally to all other
chip power inputs. The user must provide adequate external decoupling
capacitors.
Note:
These designations are package-dependent. Some packages connect all V
other internally. On those packages, all power input, except V
connections indicated in this table are minimum values; the total V
2-6
Table 2-2 Power Inputs
Description
provides isolated power for the Phase Lock Loop (PLL).
CCP
provides isolated power for the internal processing
CCQ
provides isolated power for sections of the
CCA
provides isolated power for sections of the data
CCD
provides isolated power for the bus control I/O
CCN
provides isolated power for the HI32 I/O drivers. This
CCH
CCS
DSP56305 User's Manual
power rail.
CC
provides isolated power for the ESSI,
inputs except V
CC
, are labeled V
. The number of
CCP
CC
connections are package-dependent.
CC
to each
CCP
MOTOROLA
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