Hi32 Control Register (Hctr) - Motorola DSP56305 User Manual

HOST INTERFACE (HI32)
HOST SIDE Programming Model
6.6.1

HI32 Control Register (HCTR)

31 30 29 28
15 14 13 12
HS1 HS0 HRF1
Reserved, read as zero and should be written zero
Bit
1
2
3-5
6
7
9-8
12-11
16-14
19
31-20,18-17,13,10,0 reserved
The HCTR is a 32-bit read/write control register used by the host processor to control
the HI32 interrupts, flags, semaphores, data transfer formats and operation modes.
In the PCI mode (HM=$1), the HAD31-HAD0 signals are driven with HCTR data during
a read access; and the signals are written to the HCTR in a write access.
In a 24-bit data Universal Bus mode (HM=$2 or $3 and HTF = $0 or HRF = $0), the
HD23-HD0 signals are driven with the three least significant HCTR bytes during a read
access; HD23-HD0 are written to the three least significant HCTR bytes in a write access.
In a 16-bit data Universal Bus mode (HM=$2 or $3 and HTF≠$0 or HRF≠$0), the
HD15-HD0 signals are driven with the two least significant bytes of the HCTR in a read
access; HD15-HD0 are written to the two least significant bytes of the HCTR, the most
significant portion is zero filled during the HCTR write.
6-54
27 26 25 24
11 10 9 8
HRF0 HTF1 HTF0
Name
TREQ
RREQ
HF2-HF0
DMAE
SFT
HTF1-HTF0
HRF1-HRF0
HS2-HS0
TWSD
DSP56305 User's Manual
23 22 21 20
7 6 5
SFT DMAE HF2 HF1
Function
Transmit Request Enable
Receive Request Enable
Host Flags
DMA Enable (ISA/EISA)
Slave Fetch Type
Host Transmit Data Transfer Format
Host Receive Data Transfer Format
Host Semaphores
Target Wait State Disable
19 18 17
TWSD
4 3 2 1
HF0 RREQ TREQ
MOTOROLA
16
HS2
0