Mode 0 (Real Fir Filter), Decimation By 2 - Motorola DSP56305 User Manual

12.5.5.2

Mode 0 (Real FIR Filter), Decimation by 2

The following equation is implemented:
The set up and initialization steps are the same as in Mode 0 without decimation.
Processing is also the same, except 2 'get' operations are required, so that output results
are calculated only for even indexes (see below).
Set Up
DSP
Initialization
Processing
MOTOROLA
N 1 –
∑
( )
F n =
even
i =
• Load Filter Count Register (FCNT) with (number of coefficient
values – 1)
• Choose operation mode (FOM[1:0], FDCM=0) and enable
FCOP (FEN = 1)
• Core initializes coefficients in FCM in reverse order by
executing #filter_count writes to FCIR
• Core or DMA initializes data in FDM in direct order by
executing #filter_count writes to FDIR
• Whenever FDIR is empty (FDIBE = 1), FCOP triggers core or
DMA to transfer up to four new data words to FDM via FDIR
• Compute F(n) and store result in FDOR
• FCOP triggers core or DMA for output data transfer
• Get new data word
• FCOP increments data memory pointer
• Get new data word
• FCOP increments data memory pointer
DSP56305 User's Manual
H i ( ) D n i – ⋅ ( )
0
Filter Co-Processor
Operation Modes
12-19