Clock Divider (Cd[11:0]) Sccr Bits 11–0; Clock Out Divider (Cod) Sccr Bit 12; Sci Clock Prescaler (Scp) Sccr Bit 13; Figure 8-6 16 X Serial Clock - Motorola DSP56305 User Manual

Serial Communication Interface (SCI)
SCI Programming Model
Idle Line
RX, TX Data
(SSFTD = 0)
x1 Clock
x16 Clock
(SCKP = 0)
8.3.3.1 Clock Divider (CD[11:0]) SCCR Bits 11–0
The CD[11:0] bits specify the divide ratio of the prescale divider in the SCI clock
generator. A divide ratio from 1 to 4096 (CD[11:0] = $000 to $FFF) can be selected.
Hardware and software reset clear CD[11:0].
8.3.3.2

Clock Out Divider (COD) SCCR Bit 12

The clock output divider is controlled by COD and the SCI mode. If the SCI mode is
synchronous, the output divider is fixed at divide by 2.
If the SCI mode is asynchronous, either:
• If COD is cleared and SCLK is an output (i.e., TCM and RCM are both cleared),
the SCI clock is divided by 16 before being output to the SCLK signal. Thus, the
SCLK output is a 1
• If COD is set and SCLK is an output, the SCI clock is fed directly out to the SCLK
signal. Thus, the SCLK output is a 16
The COD bit is cleared by hardware and software reset.
8.3.3.3

SCI Clock Prescaler (SCP) SCCR Bit 13

The SCP bit selects a divide by 1 (SCP is cleared) or divide by 8 (SCP is set) prescaler for
the clock divider. The output of the prescaler is further divided by 2 to form the SCI
clock. Hardware and software reset clear SCP.
8-18
0 1 2
Start

Figure 8-6 16 x Serial Clock

×
clock.
DSP56305 User's Manual
Select 8-or 9-bit Words
3 4 5 6 7
×
baud clock.
8
Stop Start
AA0692
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