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Serial Communication Interface (SCI)
SCI Programming Model
8.3.2.6
Parity Error (PE) SSR Bit 5
In the 11-bit Asynchronous modes, the PE bit is set when an incorrect parity bit has been
detected in the received character. It is set simultaneously with RDRF for the byte which
contains the parity error—that is, when the received word is transferred to the SRX. If PE
is set, further data transfer into the SRX is not inhibited. PE is cleared when the SSR is
read, followed by a read of SRX. PE is also cleared by the hardware, software, SCI
individual, or stop reset. In the 10-bit Asynchronous mode, the 11-bit Multidrop mode,
and the 8-bit Synchronous mode, the PE bit is always cleared since there is no parity bit
in these modes. If the byte received causes both parity and overrun errors, the SCI
receiver recognizes only the overrun error.
8.3.2.7
Framing Error Flag (FE) SSR Bit 6
The FE bit is set in the Asynchronous modes when no stop bit is detected in the data
string received. FE and RDRE are set simultaneously when the received word is
transferred to the SRX. However, the FE flag inhibits further transfer of data into the SRX
until it is cleared. FE is cleared when the SSR is read followed by reading the SRX. The
hardware, software, SCI individual, and stop reset also clear FE. In the 8-bit
Synchronous mode, FE is always cleared. If the byte received causes both framing and
overrun errors, the SCI receiver recognizes only the overrun error.
8.3.2.8
Received Bit 8 Address (R8) SSR Bit 7
In the 11-bit Asynchronous Multidrop mode, the R8 bit is used to indicate whether the
received byte is an address or data. R8 is set for addresses and is cleared for data. R8 is
not affected by reading the SRX or SSR. The hardware, software, SCI individual, and
stop resets clear R8.
8-16
DSP56305 User's Manual
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