Dsp Receive Data Fifo (Drxr); Dsp To Host Data Path - Motorola DSP56305 User Manual

HOST INTERFACE (HI32)
DSP SIDE Programming Model
6.5.8

DSP Receive Data FIFO (DRXR)

The 24-bit wide DSP receive data register (DRXR) is the output stage of the host-to-DSP
data path FIFO used for host-to-DSP data transfers.
The DRXR contains master data (i.e. data read by the HI32 as PCI master from an
external target) to be read if MRRQ is set in the DPSR. MRRQ is cleared if the data in the
DRXR is slave data or when the host-to-DSP data path FIFO is emptied by DSP56300
core reads. The DSP56300 core may set the MRIE bit to cause a host receive data
interrupt when MRRQ is set.
The DRXR contains slave data (i.e. data written to the HI32 from the host bus) to be read
if SRRQ is set in the DSR. SRRQ is cleared if the data in the DRXR is master data or when
the host-to-DSP data path FIFO is emptied by DSP56300 core reads. The DSP56300 core
may set the SRIE bit to cause a host receive data interrupt when SRRQ is set.
In the 32-bit mode (HM = $1 with FC = $0 or HTF = $0), only the two least significant
bytes contain data, the most significant byte is read as zeroes. (See Table 6-5 and
Table 6-15).
Hardware, software and personal software resets empty the host-to-DSP data path FIFO
(SRRQ and MRRQ are cleared).
6.5.9

DSP To Host Data Path

In PCI master data transfers (HM = $1) with FC≠$0, the master DSP-to-host data path
(DTXM-HRXM) is an eight word deep FIFO. The DSP56300 core writes to the DSP side
of the FIFO (DTXM). The data is output to the bus from the host side (HRXM).
In PCI master data transfers (HM = $1) with FC = $0, the master DSP-to-host data path is
a four word deep, 32-bit wide FIFO. The DSP56300 core writes 24-bit words to the
DTXM. Each word written by the DSP56300 core contains 16-bits of significant data,
right aligned, the most significant byte is not transmitted. The first word written by the
DSP56300 core contains the two least significant bytes of the 32-bit word to be output
from the HRXM. The second word written by the DSP56300 core contains the two most
significant bytes of the 32-bit word be output from the HRXM. Each time a 32-bit word is
output from the HRXM, the 32-bits of significant data located in two words written to
the DTXM are output.
In PCI target data transfers (HM = $1) with HRF≠$0 and in Universal Bus mode data
transfers, the slave DSP-to-host data path (DTXS-HRXS) is a six word deep FIFO. The
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