Methods Of Entering The Debug Mode; External Debug Request During Reset Assertion; External Debug Request During Normal Activity - Motorola DSP56305 User Manual

On-Chip Emulation Module

Methods of Entering the Debug Mode

Upon exiting the Debug mode, the counter is decremented after each execution of an
instruction. Interrupts are serviceable and all instructions executed, including fast
interrupt services and the execution of each repeated instruction, cause the Trace
Counter to be decremented. Upon decrementing to 0, the DSP56300 core re-enters the
Debug mode, the Trace Occurrence bit (TO) in the OSCR register is set, the core Status
bits OS[1:0] are set to 11, and the DE signal is asserted to indicate that the DSP56300 core
has entered Debug mode and is requesting service.
The OnCE Trace Counter (OTC) is a 16-bit counter that can be read or written through
the JTAG port. If N instructions are to be executed before entering the Debug mode, the
Trace Counter should be loaded with N – 1. The Trace Counter is cleared by hardware
reset.
10.7 METHODS OF ENTERING THE DEBUG MODE
Entering the Debug mode is acknowledged by the chip by setting the Core Status bits
OS1 and OS0 and asserting the DE line. This informs the external command controller
that the chip has entered the Debug mode and is waiting for commands.The DSP56300
core can disable the OnCE module if the ROM Security option is implemented. If the
ROM Security is implemented, the OnCE module remains inactive until a write
operation to the OGDBR is executed by the DSP56300 core.
10.7.1

External Debug Request During RESET Assertion

Holding the DE line asserted during the assertion of RESET causes the chip to enter the
Debug mode. After receiving the acknowledge, the external command controller must
negate the DE line before sending the first command.
Note: In this case, the chip does not execute any instruction before entering the
Debug mode.
10.7.2

External Debug Request During Normal Activity

Holding the DE line asserted during normal chip activity causes the chip to finish the
execution of the current instruction and then enter the Debug mode. After receiving the
acknowledge, the external command controller must negate the DE line before sending
the first command. This process is the same for any newly fetched instruction, including
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