Introduction; Key Features - Motorola DSP56305 User Manual

14.1

INTRODUCTION

The Cyclic Code Co-Processor (CCOP) is a peripheral module which executes cyclic
code calculations for data ciphering and deciphering and parity coding generation and
checking. The CCOP is designed to operate independently of the DSP56300 core,
requiring minimal CPU-time overhead. This peripheral is fully programmable and not
dedicated to any specific algorithm, although it is well suited for the GSM A5.x data
ciphering algorithms.
CCOP data processing occurs in four programmable CCOP Linear Feedback Shift
Registers (CFSR[A:D]). For each CFSR, there are four control registers which configure
its operation: CCOP Feedback Tap Register (CFBT[A:D]), CCOP Feedforward Tap
Register (CFFT[A:D]), CCOP Bit Select Register (CBSR[A:D]), and CCOP Mask Register
(CMSK[A:D]).
The CCOP has four operational modes, two each for cipher and parity coding. The
modes are:
• Normal Cipher Mode (CFSR[A:D] enabled)
• Step-by-step Cipher Mode (CFSR[A:D] enabled)
• Parity Coding Mode using one CFSR (CFSRA only enabled)
• Parity Coding Mode using two concatenated CFSRs (CFSRA and CFSRB enabled)
14.2

KEY FEATURES

• Contains fully programmable cyclic code engine
• Operates concurrently with the DSP56300 core with minimal CPU intervention
• Generates mask sequences for data ciphering
• Supports Fire encoding and decoding for burst error correction using any
generator polynomial of any degree up to 48
• Generates Cyclic Redundancy Code (CRC) syndrome using any generator
polynomial of any degree up to 48
• Provides a 5 × 24-bit word input/output FIFO accessible via core or DMA
MOTOROLA DSP56305 User's Manual
CYCLIC CODE CO-PROCESSOR
Introduction
14-3