Dsp56009 Features; Table 1-1 High True / Low True Signal Conventions - Motorola DSP56009 User Manual

Overview

DSP56009 Features

Table 1-1 High True / Low True Signal Conventions

Signal/Symbol
1
PIN
1
PIN
1
PIN
1
PIN
Note: PIN is a generic term for any pin on the device.
Note: Ground is an acceptable low voltage level. See the appropriate data sheet for the range of
acceptable low voltage levels (typically a TTL logic low).
Note: V is an acceptable high voltage level. See the appropriate data sheet for the range of
CC
acceptable high voltage levels (typically a TTL logic high).
1.2 DSP56009 FEATURES
The DSP56009 consists of the DSP56000 core, program and data memory, and
peripherals useful for embedded control applications. The following paragraphs
provide a list of DSP56009 features and a brief description of its core and peripheral
components.
• General Features
– Harvard architecture, with four 24-bit internal data buses and three 16-bit
internal address buses, permitting simultaneous accesses to program
memory and two data memories
– Software-programmable, Phase Lock Loop (PLL) frequency synthesizer for
the core clock with a wide range of frequency multiplications (1 to 4096)
and power-saving clock divider (2
noise
– On-Chip Emulation (OnCE™) port for unobtrusive, comprehensive,
processor speed-independent hardware/software debugging
– Stop and Wait low-power standby modes
– Efficient, object code compatible, 24-bit 56000-family DSP engine
1-6
Logic State
True
False
True
False
i
, where i = 0 to 15) for reduced clock
DSP56009 User's Manual
Signal State
Asserted
Deasserted
Asserted
Deasserted
MOTOROLA
Voltage
3
V
CC
2
Ground
2
Ground
3
V
CC