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Host Programmer Model
6.7.5
Receive Data Registers (RXH:RXM:RXL)
The host processor views the receive byte registers as three 8-bit read-only registers: the
receive high register (RXH), the receive middle register (RXM), and the receive low register
(RXL). They receive data from the high, middle, and low bytes, respectively, of the HTX
register and are selected by the external host address inputs (HA[2–0]) during a host processor
read operation. The memory address of the receive byte registers are set by ICR[HLEND]. If
ICR[HLEND] is set, the RXH is located at address $7, RXM at $6, and RXL at $5. If
ICR[HLEND] is cleared, the RXH is located at address $5, RXM at $6, and RXL at $7.
When data is transferred from the HTX register to the receive byte register at host address $7,
the ISR Receive Data Register Full (RXDF) bit is set. The host processor can program the
RREQ bit to assert the external HREQ signal when ISR[RXDF] is set. This indicates that the
HI08 has a full word (either 8, 16, or 24 bits) for the host processor. The host processor can
program the RREQ bit to assert the external HREQ signal when ISR[RXDF] is set. Assertion
of the HREQ signal informs the host processor that the receive byte registers have data to be
read. When the host reads the receive byte register at host address $7, the ISR[RXDF] bit is
cleared.
Note:
The external host should never read the RXH:RXM:RXL registers if the
ISR[RXDF] bit is cleared.
6.7.6
Transmit Data Registers (TXH:TXM:TXL)
The host processor views the transmit byte registers as three 8-bit write-only registers. These
registers are the transmit high register (TXH), the transmit middle register (TXM), and the
transmit low register (TXL). These registers send data to the high, middle, and low bytes,
respectively, of the HRX register and are selected by the external host address inputs,
HA[2–0], during a host processor write operation.
If ICR[HLEND] is set, the TXH register is located at address $7, the TXM register at $6, and
the TXL register at $5. If the HLEND bit in the ICR is cleared, the TXH register is located at
address $5, the TXM register at $6, and the TXL register at $7.
Data can be written into the transmit byte registers when the ISR transmit data register empty
(TXDE) bit is set. The host processor can program the ICR[TREQ] bit to assert the external
HREQ/HTRQ signal when ISR[TXDE] is set. This informs the host processor that the
transmit byte registers are empty. Writing to the data register at host address $7 clears the
ISR[TXDE] bit. The contents of the transmit byte registers are transferred as 24-bit data to the
HRX register when both ISR[TXDE] and HSR[HRDF] are cleared. This transfer operation
sets HSR[TXDE] and HSR[HRDF].
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DSP56303 User's Manual
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