Mitsubishi Electric MELSEC iQ-R Series User Manual page 692

No. Name
SD796 Maximum number of
blocks used for the
multiple CPU
dedicated instruction
(for CPU No.1)
SD797 Maximum number of
blocks setting used
for the multiple CPU
dedicated instruction
(for CPU No.2)
SD798 Maximum number of
blocks setting used
for the multiple CPU
dedicated instruction
(for CPU No.3)
SD799 Maximum number of
blocks setting used
for the multiple CPU
dedicated instruction
(for CPU No.4)
SD816 Basic period
SD817
SD818 Bumpless function
availability setting for
the S.PIDP
instruction
SD819 Process value output
type setting for the
S.PHPL2 instruction
SD820 Dummy device
SD821
*1 When the value out of the range is specified, operation runs while its value is being regarded as max value of each range of multiple
CPU system configuration.
APPX
690
Appendix 5 List of Special Register Areas
Data stored Details
The maximum number • The maximum number of blocks used for the multiple CPU dedicated
of blocks to be used for instruction is specified (for CPU No.1).
the dedicated • When executing the multiple CPU dedicated instruction on CPU No.1, if
instruction the number of free blocks in the dedicated instruction transfer area is less
Depending on the than the setting value on this register, SM796 is turned on.
number of CPU • This value is used as interlock signal for the continuous executions of the
modules which multiple CPU dedicated instruction.
constitute a multiple
• The maximum number of blocks used for the multiple CPU dedicated
CPU system, the
instruction is specified (for CPU No.2).
*1
range is as follows.
• When executing the multiple CPU dedicated instruction on CPU No.2, if
When constituting two
the number of free blocks in the dedicated instruction transfer area is less
modules: 2 to 599
than the setting value on this register, SM797 is turned on.
When constituting
• This value is used as interlock signal for the continuous executions of the
three modules: 2 to
multiple CPU dedicated instruction.
299
• The maximum number of blocks used for the multiple CPU dedicated
When constituting four
instruction is specified (for CPU No.3).
modules: 2 to 199
• When executing the multiple CPU dedicated instruction on CPU No.3, if
(Default: 2).
the number of free blocks in the dedicated instruction transfer area is less
than the setting value on this register, SM798 is turned on.
• This value is used as interlock signal for the continuous executions of the
multiple CPU dedicated instruction.
• The maximum number of blocks used for the multiple CPU dedicated
instruction is specified (for CPU No.4).
• When executing the multiple CPU dedicated instruction on CPU No.4, if
the number of free blocks in the dedicated instruction transfer area is less
than the setting value on this register, SM799 is turned on.
• This value is used as interlock signal for the continuous executions of the
multiple CPU dedicated instruction.
Execution cycle An execution cycle (unit: second) of process control instructions is set in
real number.
0: Enabled The availability of the bumpless function for the S.PIDP instruction is set.
1: Disabled
0: Decimal Set the output type of the process value (PV) for the S.PHPL2 instruction of
1: Percent process control instruction.
Dummy device A dummy device used in process control instructions is set.
Set by (setting
timing)
U
U
U
U
U
U
U
U