Mitsubishi Electric MELSEC iQ-R Series User Manual page 156

Master/local module
Hide thumbs Also See for MELSEC iQ-R Series:
Table of Contents

Advertisement

Precautions
■Latched devices of the CPU module
If data in latched devices of the CPU module are cleared to 0 on a program when the CPU module is powered off and on or
reset, the data may be output without being cleared to 0, depending on the timing of the cyclic data transfer processing and
link refresh.
CPU module device
Latch relay (L), file register (R, ZR)
CPU module device within the latch range
*1 For the initial device value setting of the CPU module, refer to the following.
 GX Works3 Operating Manual
9 FUNCTIONS
154
9.2 Cyclic Transmission
How to disable the device data
The device value is cleared to 0 by using the initial device value of the CPU module.
Delete all the latch range settings specified in "Latch Interval Operation Setting" under "Device Latch Interval
Setting" in "Memory/Device Setting" of "CPU Parameter".
*1

Advertisement

Table of Contents
loading

This manual is also suitable for:

Melsec iq-r cc-link ie tsn plus

Table of Contents