Itu Register Descriptions; Timer Start Register (Tstr) - Hitachi SH7032 Hardware Manual

Table 10.3 Register Configuration (cont)
Channel Name
4 (cont) Timer counter 4
General register A4
General register B4
Buffer register A4
Buffer register B4
Notes: *1 Only the values of bits A27–A24 and A8–A0 are valid; bits A23–A9 are ignored. For
details on the register addresses, see section 8.3.5, Area Descriptions.
*2 Only 0 can be written to clear flags.
10.2

ITU Register Descriptions

10.2.1

Timer Start Register (TSTR)

The timer start register (TSTR) is an eight-bit read/write register that starts and stops the timer
counters (TCNT) of channels 0–4. TSTR is initialized to H'E0 or H'60 by a reset and in standby
mode.
Bit:
Bit name:
Initial value:
R/W:
Note: * Undefined
230
Abbrevi-
ation
TCNT4
GRA4
GRB4
BRA4
BRB4
7 6 5
— — —
1 1
*
— — —
Initial
R/W Value
R/W H'00
R/W H'FF
R/W H'FF
R/W H'FF
R/W H'FF
4 3
STR4 STR3 STR2
0 0
R/W R/W R/W
Access
1
Address *
Size
H'5FFFF36 8, 16
H'5FFFF37 8, 16
H'5FFFF38 8, 16, 32
H'5FFFF39 8, 16, 32
H'5FFFF3A 8, 16, 32
H'5FFFF3B 8, 16, 32
H'5FFFF3C 8, 16, 32
H'5FFFF3D 8, 16, 32
H'5FFFF3E 8, 16, 32
H'5FFFF3F 8, 16, 32
2 1 0
STR1 STR0
0 0 0
R/W R/W