Timer Synchronization Register (Tsnc) Itu - Hitachi SH7032 Hardware Manual

Table A.11 TSTR Bit Functions
Bit Bit name
4 Counter start 4 (STR4)
3 Counter start 3 (STR3)
2 Counter start 2 (STR2)
1 Counter start 1 (STR1)
0 Counter start 0 (STR0)
A.2.11 Timer Synchronization Register (TSNC)
• Start Address: H'5FFFF01
• Bus Width: 8
Register Overview:
Bit:
Bit name:
Initial value:
R/W:
Note: * Undetermined
574
Value
0
1
0
1
0
1
0
1
0
1
7 6 5
— — —
* 1 1
— — —
Description
Count operation of TCNT4 stops
TCNT4 counts
Count operation of TCNT 3 stops
TCNT3 counts
Count operation of TCNT 2 stops
TCNT2 counts
Count operation of TCNT 1 stops
TCNT1 counts
Count operation of TCNT 0 stops
TCNT0 counts
4 3
SYNC4 SYNC3
0 0
R/W R/W
(Initial value)
(Initial value)
(Initial value)
(Initial value)
(Initial value)
2 1
SYNC2 SYNC1 SYNC0
0 0
R/W R/W
ITU
0
0
R/W