Timer Interrupt Enable Registers 0-4 (Tier0-Tier4) Itu - Hitachi SH7032 Hardware Manual

A.2.16 Timer Interrupt Enable Registers 0–4 (TIER0–TIER4)
• Start Address: H'5FFFF06 (channel 0), H'5FFFF10 (channel 1), H'5FFFF1A (channel 2),
H'5FFFF24 (channel 3), H'5FFFF34 (channel 4),
• Bus Width: 8
Register Overview:
Bit:
Bit name:
Initial value:
R/W:
Note: * Undetermined
Table A.17 TIER0–TIER4 Bit Functions
Bit Bit name
2 Overflow interrupt enable (OVIE)
1 Input capture/compare match
interrupt enable B (IMIEB)
0 Input capture/compare match
interrupt enable A (IMIEA)
580
7 6 5
— — —
1 1
*
— — —
4 3
— —
1 1
— —
Value Description
0 Interrupt request by OVF (OVI) disabled
1 Interrupt request by OVF (OVI) enabled
0 Interrupt request by IMFB (IMIB) disabled
1 Interrupt request by IMFB (IMIB) enabled
0 Interrupt request by IMFA (IMIA) disabled
1 Interrupt request by IMFA (IMIA) enabled
2 1
OVIE IMIEB IMIEA
0 0
R/W R/W R/W
(Initial value)
(Initial value)
(Initial value)
ITU
0
0