Dma Operation Register (Dmaor) - Hitachi SH7032 Hardware Manual

Bit 0: DE
0
1
9.2.5

DMA Operation Register (DMAOR)

The DMA operation register (DMAOR) is a 16-bit read/write register that controls the DMA
transfer mode. It also indicates the DMA transfer status. It is initialized to H'0000 by a reset and in
standby mode.
Bit:
Bit name:
Initial value:
R/W:
Bit:
Bit name:
Initial value:
R/W:
Note: * Write only 0 to clear the flag.
• Bits 15–10 (Reserved): These bits are always read as 0. The write value should always be 0.
• Bits 9 and 8 (Priority Mode Bits 1 and 0 (PR1 and PR0)): PR1 and PR0 select the priority level
between channels when there are simultaneous transfer requests for multiple channels.
Bit 9: PR1 Bit 8: PR0
0 0
0 1
1 0
1 1
• Bits 7–3 (Reserved): These bits are always read as 0. The write value should always be 0.
186
Description
DMA transfer disabled
DMA transfer enabled
15 14 13
—— — —
0 0
R R
7 6
— — —
0 0
R R
Description
Fixed priority order (Ch. 0 > Ch. 3 > Ch. 2 > Ch. 1) (Initial value)
Fixed priority order (Ch. 1 > Ch. 3 > Ch. 2 > Ch. 0)
Round-robin mode priority order (the priority order immediately
after a reset is Ch. 0 > Ch. 3 > Ch. 2 > Ch. 1)
External-pin round-robin mode priority order (the priority order
immediately after a reset is Ch. 3 > Ch. 2 > Ch. 1 > Ch. 0)
12 11
— —
0 0 0
R R R
5 4 3
— —
0 0 0
R R R
(Initial value)
10 9
— PR1
0 0
R R/W
2 1
AE NMIF DME
0 0
R/(W) * R/(W) *
8
PR0
0
R/W
0
0
R/W