Programmable Timing Pattern Controller And I/O Port Timing - Hitachi SH7032 Hardware Manual

CK
TCLKA–
TCLKD

(6) Programmable Timing Pattern Controller and I/O Port Timing

Table 20.10 Programmable Timing Pattern Controller and I/O Port Timing
Case A: V = 3.0 to 5.5 V, AV
CC
V = AV
SS SS
Case B: V = 5.0 V ±10%, AV
CC
V = AV
SS SS
Note: * Regular-specification products; for wide-temperature-range products, Ta = –40 to +85°C
Item
Port output delay time
Port input hold time
Port input setup time
510
t
TCKWL
Figure 20.37 ITU Clock Input Timing
= 3.0 to 5.5 V, AV
CC
= 0 V, φ = 12.5 MHz, Ta = –20 to +75°C *
= 5.0 V ±10%, AV
CC
= 0 V, φ = 20 MHz, Ta = –20 to +75°C *
Symbol
t
t
t
t
TCKS
t
TCKWH
= V
CC CC
= V
CC CC
Cases A and B
Min
—
PWD
50
PRH
50
PRS
t
TCKS
±10%, AV = 3.0 V to AV
ref
±10%, AV = 4.5 V to AV
ref
Max Unit Figure
100 ns 20.38
— ns
— ns
,
CC
,
CC