Dma Transfer Count Registers 0-3 (Tcr0-Tcr3) Dmac - Hitachi SH7032 Hardware Manual

A.2.26 DMA Transfer Count Registers 0–3 (TCR0–TCR3)
• Start Address: H'5FFFF4A (channel 0), H'5FFFF5A (channel 1), H'5FFFF6A (channel 2),
H'5FFFF7A (channel 3)
• Bus Width: 16/32
Register Overview:
Bit:
Bit name:
Initial value:
R/W:
Bit:
Bit name:
Initial value:
R/W:
Note: * Undetermined
Table A.27 TCR0–TCR3 Bit Functions
Bit Bit name
15–0 (Specifies number of DMA
transfers)
590
15 14 13
* *
R/W R/W R/W
7 6
* *
R/W R/W R/W
12 11
* * *
R/W R/W
5 4 3
* * *
R/W R/W
Description
Specifies the number of DMA transfers (bytes or
words). During DMA transfer, indicates the number of
transfers remaining.
DMAC
10 9
* *
R/W R/W R/W
2 1
* *
R/W R/W R/W
8
*
0
*