Exception Handling Operation - Hitachi SH7032 Hardware Manual

4.1.2

Exception Handling Operation

Exception sources are detected at the times indicated in table 4.1, whereupon handling starts.
Table 4.1 Exception Source Detection and Start of Handling
Exception Type
Reset Power-on
Manual
Address error
Interrupt
Instruction Trap instruction Starts when a trap instruction (TRAPA) is executed.
General illegal
instruction
Illegal slot
instruction
When exception handling begins, the CPU operates as follows:
Resets: The initial values of the program counter (PC) and stack pointer (SP) are read from the
exception vector table (the respective PC and SP values are H'00000000 and H'00000004 for a
power-on reset and H'00000008 and H'0000000C for a manual reset). For more information on the
exception vector table, see section 4.1.3, Exception Vector Table. Next, the vector base register
(VBR) is cleared to zero and interrupt mask bits (I3–I0) in the status register (SR) are set to 1111.
Program execution starts from the PC address read from the exception vector table.
Address Errors, Interrupts and Instructions: SR and PC are pushed onto the stack indicated in
R15. For interrupts, the interrupt priority level is written in the interrupt mask bits (I3–I0). For
address errors and instructions, bits I3–I0 are not affected. Next, the start address is fetched from
the exception vector table, and program execution starts from this address.
Source Detection and Start of Handling
Low-to-high transition at RES pin when NMI is high
Low-to-high transition at RES pin when NMI is low
Detected when instruction is decoded and starts after the
instruction that was executing prior to this point is completed.
Detected when instruction is decoded and starts after the
instruction that was executing prior to this point is completed.
Starts when undefined code is decoded at a position other than
directly after a delayed branch instruction (a delay slot).
Starts when undefined code or an instruction that rewrites the PC
is decoded directly after a delayed branch instruction (in a delay
slot).
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