Cpu Interface - Hitachi SH7032 Hardware Manual

• Bit 7 (Trigger Enable (TRGE)): TRGE selects whether or not to start A/D conversion when an
external trigger is input.
Bit 7 (TRGE) Description
0 When an external trigger is input, A/D conversion does not start
1 A/D conversion starts at the falling edge of an input signal from the external
trigger pin (ADTRG).
• Bits 6–0 (Reserved): These bits are always read as 1. The write value should always be 1.
14.3

CPU Interface

The A/D data registers (ADDRA–ADDRD) are 16-bit registers, but they are connected to the CPU
by an 8-bit data bus. Therefore, the upper byte of each register can be read directly, but the lower
byte is accessed through an 8-bit temporary register (TEMP).
When the CPU reads the upper byte of an A/D data register, the upper byte is transferred to the
CPU and the lower byte to TEMP. When the lower byte is accessed, the value in TEMP is
transferred to the CPU.
A program should first read the upper byte, then the lower byte of the A/D data register. This can
be performed by reading ADDR from the upper byte end using a word transfer instruction
(MOV.W, etc.). Reading only the upper byte would assure the CPU of obtaining consistent data. If
the program reads only the lower byte, however, consistent data will not be guaranteed.
Figure 14.2 shows the data flow during access to A/D data registers.
414
(Initial value)