Section 19 Power-Down State; Overview; Power-Down Modes - Hitachi SH7032 Hardware Manual

19.1

Overview

In the power-down state, all CPU functions are halted. This lowers power consumption of the SH
microprocessor dramatically.
19.1.1

Power-Down Modes

The power-down state includes the following two modes:
1. Sleep mode
2. Standby mode
Sleep mode and standby mode are entered from the program execution state according to the
transition conditions given in table 19.1. Table 19.1 also describes procedures for exiting each
mode and the states of the CPU and supporting functions.
Table 19.1 Power-Down State
Entering
Mode Procedure
Sleep Execute
mode SLEEP
instruction
with SBY bit
set to 0 in
SBYCR
Standby Execute
mode SLEEP
instruction
with SBY bit
set to 1 in
SBYCR
SBYCR: Standby control register
SBY: Standby bit
Notes: *1 Some of the registers of the on-chip supporting modules are not initialized in standby
mode. For details, see table 19.3, Register States in Standby Mode, in section 19.4.1,
Transition to Standby Mode, or the descriptions of registers given where the on-chip
supporting modules are covered.
*2 The status of I/O ports in standby mode are set by the port high-impedance bit (HIZ) in
SBYCR. See section 19.2, Standby Control Register (SBYCR), for details. The status of
pins other than the I/O ports are described in appendix B, Pin States.

Section 19 Power-Down State

Supporting
Clock CPU Functions
Runs Halted Run
Halted Halted Halted*
State
CPU
Registers RAM
Held Held
1
Held Held
I/O Exiting
Ports Procedure
Held • Interrupt
• DMA
address error
• Power-on reset
• Manual reset
Held or • NMI interrupt
2
high-Z*
• Power-on reset
• Manual reset
459