Dma Destination Address Registers 0-3 (Dar0-Dar3) Dmac - Hitachi SH7032 Hardware Manual

A.2.25 DMA Destination Address Registers 0–3 (DAR0–DAR3)
• Start Address: H'5FFFF44 (channel 0), H'5FFFF54 (channel 1), H'5FFFF64 (channel 2),
H'5FFFF74 (channel 3)
• Bus Width: 16/32
Register Overview:
Bit:
Bit name:
Initial value:
R/W:
Bit:
Bit name:
Initial value:
R/W:
Bit:
Bit name:
Initial value:
R/W:
Bit:
Bit name:
Initial value:
R/W:
Note: * Undetermined
Table A.26 DAR0–DAR3 Bit Functions
Bit Bit name
31–0 (Specifies transfer destination
address)
31 30 29
* *
R/W R/W R/W
23 22 21
* *
R/W R/W R/W
15 14 13
* *
R/W R/W R/W
7 6
* *
R/W R/W R/W
28 27
* * *
R/W R/W
20 19
* * *
R/W R/W
12 11
* * *
R/W R/W
5 4 3
* * *
R/W R/W
Description
Specifies the address of the DMA transfer destination
DMAC
26 25 24
* *
R/W R/W R/W
18 17 16
* *
R/W R/W R/W
10 9
* *
R/W R/W R/W
2 1
* *
R/W R/W R/W
*
*
8
*
0
*
589