Wait State Control - Hitachi SH7032 Hardware Manual

CK
A21–
A0
CSn
External
space
write
WR
AD15–
AD0
Internal address
Internal
On-chip
write
supporting
strobe
module
write
Internal
data bus
Internal
On-chip
read
supporting
strobe
module
read
Internal
data bus
Figure 8.34 Warp Mode Timing (Access to On-Chip Supporting Module and External
8.9

Wait State Control

The WCR1–WCR3 registers of the BSC can be set to control sampling of the WAIT signal when
accessing various areas, and the number of bus cycle states. Table 8.12 shows the number of bus
cycle states when accessing various areas.
External space writing
On-chip peripheral module read/write
T1 T2
External space address
External space
address
On-chip supporting module address
Write Cycle)
T3 T4
Write data
Write data
Read data
T5
163