Programmable Timing Pattern Controller And I/O Port Timing - Hitachi SH7032 Hardware Manual

CK
TCLKA–
TCLKD

(6) Programmable Timing Pattern Controller and I/O Port Timing

Table 20.23 Programmable Timing Pattern Controller and I/O Port Timing
Conditions: V = 3.3 V ±0.3V, AV
CC
AV , V
CC
Notes: *1 ROMless products only for 20 MHz version
*2 Regular-specification products; for wide-temperature-range products, Ta = –40 to
+85°C
Item
Port output delay time
Port input hold time
Port input setup time
CK
Ports A–C
(Read)
Ports A–C
(Write)
Figure 20.69 Programmable Timing Pattern Controller Output Timing
548
t
TCKWL
Figure 20.68 ITU Clock Input Timing
= 3.3 V ±0.3V, AV
CC
= 0 V, φ = 12.5 to 20 MHz *
= AV
SS SS
Symbol
t
t
t
T
1
t
PRS
t
TCKS
t
TCKWH
= V
CC
1
, Ta = –20 to +75°C *
Min
—
PWD
50
PRH
50
PRS
T
2
t
PRH
t
PWD
t
TCKS
±0.3V, AV = 3.0 V to
CC ref
2
Max Unit Figure
100 ns 20.69
— ns
— ns
T
3