Dram Burst Mode - Hitachi SH7032 Hardware Manual

Superh risc engine

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DRAM Burst Mode

In addition to the normal mode of DRAM access, in which row addresses are output at every

access and data then accessed (full access), the DRAM also has a high-speed page mode for use

when continuously accessing the same row. The high speed page mode enables fast access of data

simply by changing the column address after the row address is output (burst mode). Select

between full access and burst operation by setting the burst enable bit (BE)) in DCR. When the BE

bit is set to 1, burst operation is performed when the row address matches the previous DRAM

access row address. Figure 8.22 shows a comparison between full access and burst operation.

Short pitch high-speed page mode or long pitch high-speed page mode burst transfers can be

selected independently for DRAM read/write cycles even when burst operation is selected by

using the bits corresponding to area 1 in WCR1 and WCR2 (RW1, WW1, DRW1, DWW1). RAS

down mode or RAS up mode can be selected by setting the RAS down bit (RASD) in DCR when

there is an access outside the DRAM space during burst operation.

Row address 1

(a) Full access (read cycle)

Row address 1

(b) Burst operation (read cycle)

Figure 8.22 Full Access and Burst Operation

Column address 1

Row address 2

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